Semiconductor fabrication technology is well known in the art. FIG. 1A illustrates a conventional semiconductor wafer 100 comprising a plurality of product integrated circuit die sites arranged in rows and columns, an exemplary one being indicated at 102. Typically, a few product integrated circuit sites are sacrificed for process monitoring sites, an exemplary one being indicated at 104. In this case, five are shown: one near the center and the others near the center of each quadrant of the wafer. These sites typically comprise test transistors, layer minimum width and spacing structures (also known as critical dimension or CD structures), and the like to enable the foundry to characterize its process and enhance yields.
FIG. 1B shows the conventional wafer 100 with the mask reticle locations overlaid, an exemplary one being indicated at 106. Masks are used in the photo-lithographic process to construct the various individual layers that are used to fabricate the devices and interconnects comprising the product integrated circuits formed at their respective sites 102.
Typically, multiple instances of the product integrated circuits are present in the mask reticle. For each mask layer, the wafer 100 is covered with photoresist. The mask reticle is stepped over the wafer, stopping at each mask reticle location 106, where a light source of a desired frequency is flashed through the mask and onto the wafer. This develops the photoresist to define the shapes and spaces for that layer. This process is repeated for each mask reticle location 106 until the photoresist on the entire wafer has been developed.
Subsequent processing selectively removes the developed (or the undeveloped) patterns in the photoresist, leaving behind the desired shapes and spaces, which in turn are further processed to create the microscopic structures comprising the product integrated circuit die. This process is repeated for each mask layer in the fabrication process.
Thus the mask reticle sites 106 shown in FIG. 1B are an abstraction that maps the desired mask reticle locations. They are not visible on the finished wafer 100. Further, the checkerboard pattern of shading has no physical basis, and is present only to indicate the mask reticle locations in the middle of the wafer in an unobtrusive way.
FIG. 1C illustrates an enlarged portion of the conventional wafer 100 and mask reticle locations 106, including a blow-up of an exemplary conventional product integrated circuit die 108 fabricated at a particular conventional product integrated circuit die site 110. Typically, all of the conventional product integrated circuit dies formed at sites 102 are the same circuit, but this may not always be the case.
Exemplary conventional product integrated circuit 108 comprises a variety of sub-circuits that might be suitable for use in a multi-core processor targeted for a data center or enterprise level server or other high performance computing product, though the principles apply to integrated circuits suitable for many applications. Present in integrated circuit 108 are four central processing units (labeled CPU) and their associated cache memories (labeled Cache), two phase-locked loops (labeled PLL) for clock generation, four Peripheral Component Interconnect Express controllers (labeled PCIe) for interconnections to various external devices such as network interfaces, mass storage, and the like, and a power management circuit (labeled PM) for controlling five voltage regulators (labeled VR).
FIG. 2A illustrates a conventional product integrated circuit 200 targeted at an application similar to the one of conventional product integrated circuit 108 of FIG. 1C. In integrated circuit 200, the PLL, the PM, and the VR blocks have been removed, and the remaining CPU, Cache and PCIe blocks have been resized and rearranged to form a more compact circuit with a smaller die size.
FIG. 2B illustrates the conventional product integrated circuit 200 of FIG. 2A with the removed sub-circuits present as chiplets mounted upon and electrically connected to it by means of, for example, a face-to-face (F2F) or through-silicon-via (TSV) interconnect technology known in the art. The advantages of this approach are not only a smaller integrated circuit 200, but possibly a smaller package as well occupying less printed circuit board (PCB) space. Additionally, the chiplets may each be manufactured by a different foundry in a different technology—different both from each other and from the integrated circuit 200. Thus each chiplet can be optimized for its particular function regardless of the technology driving the main product integrated circuit 200. Since the chiplets are smaller, many more of them can be fabricated on a single wafer with a higher yield per chiplet due to the reduced effect of random defects.
FIG. 2C illustrates the conventional product integrated circuit 200 prior to mounting the PLL, the PM, and the VR chiplets. It shows the pad locations; an exemplary external bond pad being indicated at 208. The dotted line rectangles show outlines of the locations of the chiplets when they are attached: locations 202A and 202B for the PLL chiplets, locations 204A through 204E for the VR chiplets, and location 206A for the PM chiplet. The pads inside the dotted line rectangles are for the F2F or TSV connections to the chiplets. The dotted line rectangles themselves are illustrative only and are not physically present on conventional product integrated circuit 200.
The smallest standard pad pitch for probe testing is about 20 micro-meters (or microns) and the size of many chiplets will be limited by the pad pitch (instead of the functional circuitry), thus increasing their cost. Smaller pitch interconnect technologies are known in the art like, for example, Direct Bond Interconnect (DBI®) from Ziptronix, Inc. and Invensas Corporation which attaches chiplets to wafers by means of a room temperature dielectric bonding technology followed by low temperature annealing. During the anneal, metal present at or just below the dielectric bond material on both sides of the bond will expand slightly thus creating a reliable electrical connection. This technology is typically employed with an interconnect pad pitch of three microns to six microns, has been proven at 1.6 microns, and has the potential to scale to below one micron.
Once the chiplets have been attached to integrated circuit 200, it can be tested using conventional techniques much as those that would be employed to test conventional product integrated circuit 108. If a defective chiplet were to be attached to integrated circuit 200 the entire assembly including the chiplets might need to be scrapped, so there is a need for testing the chiplets before they can be mounted on integrated circuit 200.
Since the chiplets are directly attached to integrated circuit 200 without a package, they must be tested before the wafer sawing or plasma dicing step which separates them into individual chiplets. (Plasma dicing is analogous to plasma etching used to make trenches on the surface of an integrated circuit, except the trenches are deep enough to singulate the chiplets.) The reduced pad pitch and fragility of the smaller pads make this challenging. At best a fraction of the pads could be probed at one time limiting test coverage, and the probes would damage the contacted pads sufficiently that the wafer would need to be returned to the fab for further processing to repair the surface damage across the entire wafer. This approach is undesirable since it significantly increases the manufacturing cost of the chiplets.